The present invention relates to a static random access memory system and to a control method for the static random access memory system, and more particularly, to a static random access memory system used within a microprocessor and to a control method for the static random access memory system.
For computer systems often using micro-processing units (MPUs), reducing the power consumption of a static random access memory (SRAM) custom macro within such an MPU is known as an efficient method for reducing the power consumption of the MPU.
Much research on reducing power consumption has been conducted and made public. For example, a method for reducing power consumption by managing a line of a cache memory using a counter and stopping power supply to a line that was last accessed more than a predetermined time ago is known. This method exploits the fact that temporal locality exists in program access. However, if the power supply to a line is stopped, the value of the line is lost (the value cannot be read from the line). Thus, there is a need to store the value by copying the value in a main memory or the like.
In addition, a method for reducing power consumption by applying a low voltage to a cache line when a cache memory is not used is known. In this method, power supply is performed at a level at which the cache memory can store a value, and thus the value is not lost, unlike in the above-mentioned method. The reduction in the power consumption is achieved by a simple algorithm in which a cache line periodically enters a sleep mode (drowsy mode). However, in a case where a cache line changes from the sleep mode to a normal access mode, penalty (processing for avoiding an instable operation of a system due to power activation or the like) occurs within one or two cycles. The cache line is returned to the normal access mode within one or two cycles (the power-supply voltage is increased to a normal voltage so that an SRAM can be operated with that power supply). Since a voltage is reduced to a low level such that a value can be stored, this method has drawbacks, such as variations in semiconductors (in terms of a variation in threshold voltages and a variation in the existence of a process corner) and susceptibility to noise.
In addition, a method for configuring a cache memory using a variable threshold voltage complementary metal-oxide semiconductor (VT-CMOS) and performing power control for individual cache lines is known. However, a long time is required for power activation and voltage stabilization for a line. Thus, this method has a drawback, such as a significant elongation of the time required for accessing an SRAM.
In addition, a method for reducing the power consumption of a line not being used while maintaining performance by constantly supplying power to a cache line to which access is often made is known. However, in the cache memory configuration, a power control counter and a power control circuit are provided in a tag memory portion for each of a plurality of entries. Thus, this method has a drawback, such as an increase in the circuit scale.
In addition, a method for performing program profile-based power control in accordance with a cache decay is known. In this method, the decay interval of a cache memory is changed by profiling a program. However, the value of an SRAM, power supply to which is stopped, must be stored by copying the value in a main memory or the like. Furthermore, profile information is necessary for the execution of power control.
The above-mentioned methods have been proposed in the view of “how the power consumption in an SRAM can be reduced”. That is, the above-mentioned methods are based on a concept in which in order to reduce power consumption, power supply is stopped, resulting in the possible loss of data or a concept in which in order to reduce power consumption, the amount of leak current is reduced by reducing a voltage to a level such that data can be stored.
In addition, as described above, in a case where a circuit is implemented using a known method, there are two main problems.
(1) A normal power-supply voltage state must be returned from a power-supply stopped state or a low-voltage application state, and a state exhibiting a stable power supply must be reached. In recent high-frequency microprocessors, waiting for reaching a stable state wastes time.
(2) A small power-control memory element and a control circuit for the memory element must be provided for each tag entry of a cache tag in a cache SRAM, thus increasing the circuit scale.